The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having clock generation circuits therein.
Integrated circuit devices frequently utilize internal clock generators to synchronize the timing of internal operations within the devices. In many applications, an internal clock generator utilizes a delay locked loop (or phase locked loop) that operates to synchronize an internal clock signal to a clock signal received from external the device (i.e., an external clock signal). In FIG. 1, a conventional delay locked loop (DLL) integrated circuit 10 is illustrated. This DLL integrated circuit 10 may be utilized within many devices requiring synchronous operation, including memory devices such as synchronous dynamic random access memory (SDRAM) devices.
The DLL integrated circuit 10 of FIG. 1 includes a phase detector 14, a DLL control block 16, a DLL analog block 18 and a compensation delay unit 12. As illustrated, the phase detector 14 is responsive to a primary clock signal (CLK), which may be an external clock signal, and a feedback clock signal (FCLK). The phase detector 14 is configured to generate an up/down control signal (UP/DN) in response to detecting a positive or negative phase difference between the primary clock signal CLK and the feedback clock signal FCLK. The up/down control signal UP/DN may be a multi-bit digital signal, as shown, or an analog signal. The DLL control block 16 is illustrated as being responsive to the up/down control signal UP/DN and a driving clock signal (DCLK), which may have the same period as the primary clock signal CLK and may even be derived from the primary clock signal using on-chip circuitry (not shown) that is associated with the DLL integrated circuit 10. The DLL control block 16 is illustrated as generating a multi-bit digital control signal (CON) in response to the driving clock signal DCLK and the up/down control signal UP/DN. As will be understood by those skilled in the art, the control signal CON may be synchronized to the driving clock signal DCLK and may have a binary value that increases in response to a positive (negative) up/down control signal UP/DN and decreases in response to a negative (positive) up/down control signal UP/DN. Because the control signal CON is synchronized to the driving clock signal DCLK, the frequency of the driving clock signal DCLK typically sets the frequency at which the control signal CON is updated with a new value.
The DLL analog block 18 may comprise a conventional delay line having a variable length that is set by the value of the control signal CON. Alternatively, the delay line may have a fixed length and the control signal CON may operate to adjust the delay of each delay element in the chain. This delay line is configured to generate the internal clock signal (ICLK) in response the primary clock signal CLK, which is received at an input of the delay line. A compensation delay unit 12, which may include a fixed length delay line, is provided in a feedback path of the DLL integrated circuit 10. As illustrated, the compensation delay unit 12 generates the feedback clock signal FCLK in response to the internal clock signal ICLK. Accordingly, changes in the phase of the internal clock signal ICLK may be reflected as equivalent changes in the phase of the feedback clock signal FCLK. The compensation delay unit 12 may not be provided in some conventional DLL integrated circuits.
Unfortunately, if the feedback clock signal FCLK or primary clock signal CLK experience excessive phase jitter as a result of noise or other transient disturbance, this excessive phase jitter may manifest itself as a significant change in the value of the up/down control signal UP/DN and a significant change in the value of the control signal CON. Such large changes in the value of these control signals may significantly influence the phase of the internal clock signal ICLK and may cause timing errors within the integrated circuit device by reducing the timing budgets associated with the operation of synchronous device elements.
There are many known factors that may cause excessive phase jitter in a clock signal. For example, FIG. 2 illustrates how certain active, read and/or write commands within an integrated circuit memory device may cause abrupt power supply fluctuations (i.e., power supply noise). Such power supply fluctuations may operate to vary the effective delay provided by the compensation delay unit 12 and/or DLL analog block 18 illustrated by FIG. 1. These delay changes may result in large xe2x80x9ctransientxe2x80x9d phase differences between the primary clock signal CLK (e.g., external clock signal) and the feedback clock signal FCLK. FIG. 3 illustrates another example of how excessive phase jitter may occur. In particular, FIG. 3 illustrates a system board 20 having a memory controller 22 that generates a synchronizing clock signal CLK and a memory device 24 (e.g., SDRAM) that receives the clock signal CLK and synchronizes internal operations to the received clock signal CLK. As illustrated, when operating at high frequency, the memory controller 22 may generate a clock signal CLK that is susceptible to abrupt jitter when passing from the output pins of the memory controller 22 to the input pins of the memory device 24. Accordingly, in response to this abrupt jitter, the phase detector 14 illustrated by FIG. 1 may generate an excessively large change in the value of the up/down control signal UP/DN, even though the abrupt jitter represents only a short duration transient to a normal operating condition where the primary clock signal CLK and feedback clock signal FCLK are otherwise locked in phase with each other.
Attempts have been made to address phase jitter errors in DLL and PLL integrated circuits. For example, U.S. Pat. No. 6,133,783 to Stockman et al. describes a phase jitter canceller that improves the operation of a PLL integrated circuit. U.S. Pat. No. 6,434,083 to Lim describes a DLL integrated circuit that generates a complementary pair of feedback clock signals to support high speed operation. The disclosures of the ""783 and ""083 patents, which are assigned to the present assignee, are hereby incorporated herein by reference.
Notwithstanding the above-described attempts to develop high performance DLL and PLL integrated circuit devices, there continues to be a need for improved delay locked loop DLL (and PLL) integrated circuits having less susceptibility to phase jitter.
Embodiments of the present invention operate to prevent excessive phase jitter associated with a clock signal or other periodic control signal from adversely influencing the operation of circuit elements that are controlled by the clock signal or other periodic control signal. According to one embodiment of the present invention, an integrated circuit device is provided that includes at least one delay element and a control circuit that is configured to periodically adjust a delay of said at least one delay element in response to a first clock signal (CLK). This first clock signal may be a primary clock signal, such as an external clock signal received by the integrated circuit device. The control circuit is further configured to block at least one periodic adjustment of the delay of the at least one delay element in response to detecting excessive jitter with the first clock signal (CLK). In this embodiment, the at least one delay element and the control circuit may collectively define a delay locked loop (DLL). This DLL may be configured to block at least one periodic adjustment to a phase of an internal clock signal (ICLK) in response to detecting an excessive phase difference between the first clock signal (CLK) and a feedback clock signal (FCLK) derived from the internal clock signal (ICLK). In particular, this periodic adjustment may be blocked by halting at least one periodic adjustment to the phase of the internal clock signal (ICLK) that is triggered in response to a leading edge of a driving clock signal (DCLK). This driving clock signal (DCLK) may have the same period as the first clock signal (CLK) and may even be derived from the first clock signal (CLK). The control circuit may also be configured so that in the absence of the excessive phase difference, the delay of the at least one delay element is adjusted at a frequency equal to a frequency of the driving clock signal (DCLK).
According to another embodiment of the present invention, the at least one delay element and the control circuit collectively define a percent-of-clock delay circuit (e.g., 20%-of-clock) that can be configured using master and slave delay lines. In this embodiment, the slave delay line may be configured to receive a periodic signal that is to be delayed in time by an amount equal to some percentage of a primary clock signal. Alternatively, the slave delay line may be configured to receive the primary clock signal and provide a percent-of-clock delay to the primary clock signal.
In still further embodiments of the present invention, a delay locked loop (DLL) is configured to block at least one periodic adjustment to a phase of an internal clock signal in response to detecting an excessive phase difference between an incoming clock signal and a feedback clock signal derived from the internal clock signal. Moreover, in response to an excessive phase difference that is sustained, the DLL is configured to resume periodic adjustment to the phase of the internal clock signal until the phase difference between the incoming clock signal and the feedback clock signal returns to an acceptable level.
In yet other embodiments of the present invention, a delay locked loop (DLL) is configured to generate an outgoing clock signal in response to an incoming clock signal. The DLL includes a phase detector that is configured to compare a phase of the incoming clock signal with a phase of a feedback clock signal that is derived from the outgoing clock signal. The DLL also includes a variable delay element (e.g., variable delay line) that is configured to generate the outgoing clock signal in response to at least a first time-varying control signal (e.g., multi-bit control signal) and the incoming clock signal. Here, the DLL also includes a control circuit, which operates as means, responsive to the incoming clock signal and the feedback clock signal, for generating an active halt signal that blocks at least one periodic update of a delay provided by the variable delay element in response to detecting an excessive phase difference between the incoming and feedback clock signals.